1. Field of the Invention
The present invention relates in general to the field of data processing. In one aspect, the present invention relates to a method and system for reducing power consumption in a digital processor.
2. Description of the Related Art
In general, data processors are capable of executing a variety of instructions. Processors are used in a variety of applications, including communication systems formed with wireless and/or wire-lined communication devices. Such communication systems range from national and/or international cellular telephone systems to the Internet to point-to-point in-home wireless networks. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, wireless communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), digital amps, global system for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel-multi-point distribution systems (MMDS) and/or variations thereof. Especially with wireless and/or mobile communication devices (such as a cellular telephone, two-way radio, personal digital assistant (PDA), personal computer (PC), laptop computer, home entertainment equipment, etc.), the processor or processors in a device must be able to run various complex communication programs using only a limited amount of power that is provided by power supplies, such as batteries, contained within such devices. Because of the computational intensity (and the associated power consumption by the processor(s)) for communication functions, it is an important goal in the design of wireless and/or mobile communication devices to minimize processor and other module operations (and the associated power consumption). It is particularly crucial for mobile applications in order to extend battery life.
With conventional solutions for saving power, a variety of complex circuit and software designs have been proposed. These mechanisms typically implement CPU clock management by switching between an active mode and an idle mode. In the idle mode, the processor has no work to do and the CPU stops its clocking and waits for an interrupt. The CPU reverts back to active mode whenever it has work to do, and in this active mode, the CPU resumes its maximum pre-configured clock speed. This approach exhibits substantial latencies for entering and leaving the idle mode, which restricts the power that can be saved and the range of applicability because these latencies may preclude a processor from being able to deactivate modules before having to reactivate them. Moreover, these mechanisms are inefficient, in that they over-react to processing activity by placing the CPU clock in either a fully “on” or fully “off” state, or otherwise provide only limited or predetermined clock frequency modes of operation. Other mechanisms, such as implemented with iPAQ, Intel SpeedStep and AMD PowerNow! devices, use software to control the CPU frequency or voltage, though a major problem with this approach is that the load estimating software itself creates an extra load on the CPU, reducing the power saving benefits of such an approach. Software-based frequency control also suffers from response time latencies that can impede real-time performance requirements, especially when implemented with complex signaling mechanisms and processor state transitions which require significant hardware and software support.
In addition to the complexity of the computational requirements for a communications processor, such as described above, the ever-increasing need for higher speed communications systems imposes additional performance requirements and resulting costs for communications systems. In order to reduce costs, communications systems are increasingly implemented using Very Large Scale Integration (VLSI) techniques. The level of integration of communications systems is constantly increasing to take advantage of advances in integrated circuit manufacturing technology and the resulting cost reductions. This means that communications systems of higher and higher complexity are being implemented in a smaller and smaller number of integrated circuits. For reasons of cost and density of integration, the preferred technology is CMOS. To this end, digital signal processing (“DSP”) techniques generally allow higher levels of complexity and easier scaling to finer geometry technologies than analog techniques, as well as superior testability and manufacturability.
Therefore, a need exists for a method and apparatus that provides reduced power consumption with a more efficient CPU clocking scheme. In addition, a need exists for reducing processor power consumption without requiring complex hardware and elaborate signaling mechanisms. Moreover, a need exists for improved selectivity when adjusting the clock frequency or voltage levels during runtime operations. There is also a need for a better system that is capable of performing the above functions and overcoming these difficulties without increasing circuit area, operational power and software overhead. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.